What is wrong with my LDO?

[matthewn2002]

Hi everyone,

I'm an ee student trying to study power electronics on my own. I'm designing a basic LDO to solidify my understanding, but something is wrong and I'm not sure what. Below is my circuit and simulation, if anyone has any feedback, I'd much appreciate it!

Node 1 (Green) - Input Voltage
Node 2 (Blue) - Output Voltage
Node 3 (Red) - Voltage on the non inverting side of op amp
Node 4 (Cyan) - Output of op amp

 

[EE_Goodman]

From the looks of your circuit and simulation, it seems like your op amp is acting like a comparator and is likely railed at its negative supply, which is a common issue.
You're trying to use a PMOS as the pass element, which is a good choice for an LDO. However, the op amp isn't set up to drive it correctly. You need to use a feedback loop to create a reference voltage and compare it to the output voltage.
The op amp output should then drive the gate of the PMOS to regulate the output voltage.
Your current simulation shows the output voltage at around 2.5V, and the op amp output is railed at -12V, which means your PMOS is fully on. The op amp isn't regulating the output because it can't drive the gate any lower.
You need to connect the op amp's non-inverting input to a voltage reference and its inverting input to the output voltage.
The op amp's output should then be connected to the gate of the PMOS to form a proper feedback loop.
This will allow it to adjust the gate voltage and maintain a constant output.

 

[RichSj1]

V4 is wrong side.